gnu: yosys: Do not propagate any inputs.
* gnu/packages/fpga.scm (yosys)[arguments]<#:phases>: Patch reference to z3 in "fix-paths" phase; in "use-external-abc" phase, use complete path to "abc" executable in store. [propagated-inputs]: Remove, moving abc and z3 from here... [inputs]: ...to here. Signed-off-by: Christopher Baines <mail@cbaines.net>master
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9b1d051e6f
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@ -159,6 +159,9 @@ For synthesis, the compiler generates netlists in the desired format.")
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#~(modify-phases %standard-phases
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(add-before 'configure 'fix-paths
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* "./backends/smt2/smtio.py"
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(("\\['z3")
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(string-append "['" (search-input-file inputs "/bin/z3"))))
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(substitute* "./passes/cmds/show.cc"
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(("exec xdot")
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(string-append "exec " (search-input-file inputs
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@ -171,9 +174,11 @@ For synthesis, the compiler generates netlists in the desired format.")
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(lambda* (#:key make-flags #:allow-other-keys)
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(apply invoke "make" "config-gcc" make-flags)))
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(add-after 'configure 'use-external-abc
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(lambda _
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* '("./Makefile")
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(("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
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(("ABCEXTERNAL \\?=")
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(string-append "ABCEXTERNAL = "
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(search-input-file inputs "/bin/abc"))))))
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(add-before 'check 'fix-iverilog-references
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(lambda* (#:key inputs native-inputs #:allow-other-keys)
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(let ((iverilog (search-input-file (or native-inputs inputs)
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@ -211,15 +216,14 @@ For synthesis, the compiler generates netlists in the desired format.")
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python
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tcl)) ; tclsh for the tests
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(inputs
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(list graphviz
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(list abc
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graphviz
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libffi
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psmisc
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readline
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tcl
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xdot))
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(propagated-inputs
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(list abc
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z3)) ; should be in path for yosys-smtbmc
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xdot
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z3))
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(home-page "https://yosyshq.net/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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