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gnu: yosys: Do not propagate any inputs. 

* gnu/packages/fpga.scm (yosys)[arguments]<#:phases>: Patch reference to z3 in
"fix-paths" phase; in "use-external-abc" phase, use complete path to "abc"
executable in store.
[propagated-inputs]: Remove, moving abc and z3 from here...
[inputs]: ...to here.

Signed-off-by: Christopher Baines <mail@cbaines.net>
master
Simon South 2023-02-10 08:16:54 -05:00 committed by Christopher Baines
parent 9b1d051e6f
commit ade3bfd036
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GPG Key ID: 5E28A33B0B84F577
1 changed files with 11 additions and 7 deletions
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gnu/packages/fpga.scm
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@ -159,6 +159,9 @@ For synthesis, the compiler generates netlists in the desired format.")
#~(modify-phases %standard-phases #~(modify-phases %standard-phases
(add-before 'configure 'fix-paths (add-before 'configure 'fix-paths
(lambda* (#:key inputs #:allow-other-keys) (lambda* (#:key inputs #:allow-other-keys)
(substitute* "./backends/smt2/smtio.py"
(("\\['z3")
(string-append "['" (search-input-file inputs "/bin/z3"))))
(substitute* "./passes/cmds/show.cc" (substitute* "./passes/cmds/show.cc"
(("exec xdot") (("exec xdot")
(string-append "exec " (search-input-file inputs (string-append "exec " (search-input-file inputs
@ -171,9 +174,11 @@ For synthesis, the compiler generates netlists in the desired format.")
(lambda* (#:key make-flags #:allow-other-keys) (lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags))) (apply invoke "make" "config-gcc" make-flags)))
(add-after 'configure 'use-external-abc (add-after 'configure 'use-external-abc
(lambda _ (lambda* (#:key inputs #:allow-other-keys)
(substitute* '("./Makefile") (substitute* '("./Makefile")
(("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc")))) (("ABCEXTERNAL \\?=")
(string-append "ABCEXTERNAL = "
(search-input-file inputs "/bin/abc"))))))
(add-before 'check 'fix-iverilog-references (add-before 'check 'fix-iverilog-references
(lambda* (#:key inputs native-inputs #:allow-other-keys) (lambda* (#:key inputs native-inputs #:allow-other-keys)
(let ((iverilog (search-input-file (or native-inputs inputs) (let ((iverilog (search-input-file (or native-inputs inputs)
@ -211,15 +216,14 @@ For synthesis, the compiler generates netlists in the desired format.")
python python
tcl)) ; tclsh for the tests tcl)) ; tclsh for the tests
(inputs (inputs
(list graphviz (list abc
graphviz
libffi libffi
psmisc psmisc
readline readline
tcl tcl
xdot)) xdot
(propagated-inputs z3))
(list abc
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/") (home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer") (synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.") (description "Yosys synthesizes Verilog-2005.")