607 lines
23 KiB
Scheme
607 lines
23 KiB
Scheme
;;; GNU Guix --- Functional package management for GNU
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;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
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;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org>
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;;; Copyright © 2018–2021 Tobias Geerinckx-Rice <me@tobias.gr>
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;;; Copyright © 2019 Amin Bandali <bandali@gnu.org>
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;;; Copyright © 2020 Vinicius Monego <monego@posteo.net>
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;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw>
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;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au>
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;;; Copyright © 2022 jgart <jgart@dismail.de>
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;;;
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;;; This file is part of GNU Guix.
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;;;
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;;; GNU Guix is free software; you can redistribute it and/or modify it
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;;; under the terms of the GNU General Public License as published by
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;;; the Free Software Foundation; either version 3 of the License, or (at
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;;; your option) any later version.
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;;;
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;;; GNU Guix is distributed in the hope that it will be useful, but
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;;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;;; GNU General Public License for more details.
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;;;
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;;; You should have received a copy of the GNU General Public License
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;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
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(define-module (gnu packages fpga)
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#:use-module ((guix licenses) #:prefix license:)
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#:use-module (guix gexp)
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#:use-module (guix packages)
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#:use-module (guix download)
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#:use-module (guix git-download)
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#:use-module (guix utils)
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#:use-module (guix build-system gnu)
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#:use-module (guix build-system cmake)
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#:use-module (guix build-system python)
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#:use-module (gnu packages)
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#:use-module (gnu packages autotools)
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#:use-module (gnu packages base)
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#:use-module (gnu packages compression)
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#:use-module (gnu packages elf)
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#:use-module (gnu packages pkg-config)
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#:use-module (gnu packages tcl)
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#:use-module (gnu packages readline)
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#:use-module (gnu packages python)
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#:use-module (gnu packages python-xyz)
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#:use-module (gnu packages bison)
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#:use-module (gnu packages check)
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#:use-module (gnu packages flex)
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#:use-module (gnu packages gettext)
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#:use-module (gnu packages gtk)
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#:use-module (gnu packages graphviz)
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#:use-module (gnu packages libffi)
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#:use-module (gnu packages linux)
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#:use-module (gnu packages llvm)
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#:use-module (gnu packages maths)
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#:use-module (gnu packages perl)
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#:use-module (gnu packages ghostscript)
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#:use-module (gnu packages gperf)
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#:use-module (gnu packages gawk)
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#:use-module (gnu packages version-control)
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#:use-module (gnu packages qt)
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#:use-module (gnu packages boost)
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#:use-module (gnu packages algebra)
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#:use-module (gnu packages libftdi)
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#:use-module (gnu packages libusb))
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(define-public abc
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(let ((commit "70cb339f869e")
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(revision "2"))
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(package
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(name "abc")
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(version (git-version "0.0" revision commit))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/berkeley-abc/abc")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"1ngxg4jvz8vwm74sbidysgz3v5lrzjcabkqj4nhcksi6hnhyc9m8"))))
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(build-system gnu-build-system)
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(inputs
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(list readline))
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(arguments
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(list #:license-file-regexp "copyright.txt"
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#:tests? #f ; no tests
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#:phases
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#~(modify-phases %standard-phases
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(delete 'configure)
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(replace 'install
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(lambda _
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(install-file "abc" (string-append #$output "/bin")))))))
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(home-page "https://people.eecs.berkeley.edu/~alanmi/abc/")
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(synopsis "Sequential logic synthesis and formal verification")
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(description "ABC is a program for sequential logic synthesis and
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formal verification.")
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(license
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(license:non-copyleft
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"https://people.eecs.berkeley.edu/~alanmi/abc/copyright.htm")))))
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(define-public iverilog
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(package
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(name "iverilog")
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(version "11.0")
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(source (origin
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(method url-fetch)
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(uri
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(string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
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"verilog-" version ".tar.gz"))
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(sha256
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(base32
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"1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
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(build-system gnu-build-system)
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(arguments
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`(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
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(native-inputs
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(list flex bison ghostscript zlib)) ; ps2pdf
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(home-page "http://iverilog.icarus.com/")
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(synopsis "FPGA Verilog simulation and synthesis tool")
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(description "Icarus Verilog is a Verilog simulation and synthesis tool.
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It operates as a compiler, compiling source code written in Verilog
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(IEEE-1364) into some target format.
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For batch simulation, the compiler can generate an intermediate form
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called vvp assembly.
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This intermediate form is executed by @command{vvp}.
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For synthesis, the compiler generates netlists in the desired format.")
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;; GPL2 only because of:
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;; - ./driver/iverilog.man.in
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;; - ./iverilog-vpi.man.in
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;; - ./tgt-fpga/iverilog-fpga.man
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;; - ./vvp/vvp.man.in
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;; Otherwise would be GPL2+.
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;; You have to accept both GPL2 and LGPL2.1+.
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(license (list license:gpl2 license:lgpl2.1+))))
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(define-public yosys
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(package
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(name "yosys")
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(version "0.26")
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/yosys")
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(commit (string-append "yosys-" version))))
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(sha256
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(base32
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"0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
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(file-name (git-file-name name version))))
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(build-system gnu-build-system)
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(arguments
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(list
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#:test-target "test"
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#:make-flags #~(list "CC=gcc"
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"CXX=g++"
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(string-append "PREFIX=" #$output))
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#:phases
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#~(modify-phases %standard-phases
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(add-before 'configure 'fix-paths
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* "./backends/smt2/smtio.py"
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(("\\['z3")
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(string-append "['" (search-input-file inputs "/bin/z3"))))
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(substitute* "./kernel/fstdata.cc"
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(("vcd2fst")
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(search-input-file inputs "/bin/vcd2fst")))
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(substitute* '("./passes/cmds/show.cc"
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"./passes/cmds/viz.cc")
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(("exec xdot")
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(string-append "exec " (search-input-file inputs
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"/bin/xdot")))
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(("dot -")
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(string-append (search-input-file inputs "/bin/dot") " -"))
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(("fuser")
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(search-input-file inputs "/bin/fuser")))))
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(replace 'configure
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(lambda* (#:key make-flags #:allow-other-keys)
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(apply invoke "make" "config-gcc" make-flags)))
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(add-after 'configure 'use-external-abc
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* '("./Makefile")
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(("ABCEXTERNAL \\?=")
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(string-append "ABCEXTERNAL = "
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(search-input-file inputs "/bin/abc"))))))
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(add-after 'install 'add-symbolic-link
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(lambda* (#:key inputs #:allow-other-keys)
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;; Previously this package provided a copy of the "abc"
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;; executable in its output, named "yosys-abc". Create a
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;; symbolic link so any external uses of that name continue to
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;; work.
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(symlink (search-input-file inputs "/bin/abc")
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(string-append #$output "/bin/yosys-abc"))))
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(add-after 'install 'wrap
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(lambda* (#:key inputs #:allow-other-keys)
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(wrap-program (string-append #$output "/bin/yosys-witness")
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`("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
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(native-inputs
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(list bison
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flex
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gawk ; for the tests and "make" progress pretty-printing
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iverilog ; for the tests
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pkg-config
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python
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tcl)) ; tclsh for the tests
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(inputs
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(list abc
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graphviz
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gtkwave
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libffi
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psmisc
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readline
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tcl
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xdot
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z3
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zlib
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python
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python-click))
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(home-page "https://yosyshq.net/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(license license:isc)))
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(define-public icestorm
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(let ((commit "2bc541743ada3542c6da36a50e66303b9cbd2059")
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(revision "4"))
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(package
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(name "icestorm")
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(version (git-version "0.0" revision commit))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/cliffordwolf/icestorm")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"0d0ibdq3rzmjcbv97h4b9wgq8ikvgwlfw60spi2w81mis317lis8"))))
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(build-system gnu-build-system)
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(arguments
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`(#:tests? #f ; no unit tests that don't need an FPGA exist.
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#:make-flags (list "CC=gcc" "CXX=g++"
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(string-append "PREFIX=" (assoc-ref %outputs "out")))
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#:phases
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(modify-phases %standard-phases
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(add-after 'unpack 'remove-usr-local
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(lambda _
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(substitute* "iceprog/Makefile"
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(("-I/usr/local/include") "")
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(("-L/usr/local/lib") ""))
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#t))
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(add-after 'remove-usr-local 'fix-usr-local
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(lambda* (#:key outputs #:allow-other-keys)
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(substitute* "icebox/icebox_vlog.py"
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(("/usr/local/share") (string-append (assoc-ref outputs "out") "/share")))
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#t))
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(delete 'configure))))
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(inputs
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(list libftdi))
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(native-inputs
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`(("python-3" ,python)
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("pkg-config" ,pkg-config)))
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(home-page "https://www.clifford.at/icestorm/")
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(synopsis "Project IceStorm - Lattice iCE40 FPGAs bitstream tools")
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(description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools.
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Includes the actual FTDI connector.")
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(license license:isc))))
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(define-public nextpnr-ice40
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(let [(commit "fbe486df459909065d6852a7495a212dfd2accef")
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(revision "1")]
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(package
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(name "nextpnr-ice40")
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(version (git-version "0.0.0" revision commit))
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "git://github.com/YosysHQ/nextpnr")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"1fmxsywgs45g88ra7ips5s2niiiwrkyxdcy742ws18dfk2y4vi9c"))))
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(inputs
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(list boost
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eigen
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icestorm
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python
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qtbase-5
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yosys))
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(build-system cmake-build-system)
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(arguments
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`(#:configure-flags `("-DARCH=ice40"
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,(string-append "-DICEBOX_ROOT="
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(assoc-ref %build-inputs "icestorm")
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"/share/icebox"))
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#:tests? #f))
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(synopsis "Place-and-Route tool for FPGAs")
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(description "Nextpnr aims to be a vendor neutral, timing driven,
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FOSS FPGA place and route tool.")
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(home-page "https://github.com/YosysHQ/nextpnr")
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(license license:expat))))
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(define-public arachne-pnr
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(let ((commit "840bdfdeb38809f9f6af4d89dd7b22959b176fdd")
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(revision "2"))
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(package
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(name "arachne-pnr")
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(version (string-append "0.0-" revision "-" (string-take commit 9)))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/arachne-pnr")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"1dqvjvgvsridybishv4pnigw9gypxh7r7nrqp9z9qq92v7c5rxzl"))))
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(build-system gnu-build-system)
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(arguments
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`(#:test-target "test"
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#:make-flags
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(list (string-append "DESTDIR=" (assoc-ref %outputs "out"))
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(string-append "ICEBOX=" (string-append
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(assoc-ref %build-inputs "icestorm")
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"/share/icebox")))
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#:phases (modify-phases %standard-phases
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(replace 'configure
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(lambda* (#:key outputs inputs #:allow-other-keys)
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(substitute* '("./tests/fsm/generate.py"
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"./tests/combinatorial/generate.py")
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(("#!/usr/bin/python") "#!/usr/bin/python2"))
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#t)))))
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(inputs
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(list icestorm))
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(native-inputs
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`(("git" ,git) ; for determining its own version string
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("yosys" ,yosys) ; for tests
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("perl" ,perl) ; for shasum
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("python-2" ,python-2))) ; for tests
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(home-page "https://github.com/YosysHQ/arachne-pnr")
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(synopsis "Place-and-Route tool for FPGAs")
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(description "Arachne-PNR is a Place-and-Route Tool For FPGAs.")
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(license license:gpl2))))
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(define-public gtkwave
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(package
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(name "gtkwave")
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(version "3.3.113")
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(source
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(origin
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(method url-fetch)
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(uri (list (string-append "mirror://sourceforge/gtkwave/"
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"gtkwave-" version "/"
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"gtkwave-" version ".tar.gz")
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(string-append "https://gtkwave.sourceforge.net/"
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"gtkwave-" version ".tar.gz")))
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(sha256
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(base32 "1zqkfchmns5x90qxa8kg39bfhax3vxf1mrdz3lhyb9fz1gp4difn"))))
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(build-system gnu-build-system)
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(native-inputs
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(list gperf pkg-config))
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(inputs
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(list tcl tk gtk+-2))
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(arguments
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(list #:configure-flags
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#~(list (string-append "--with-tcl="
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(assoc-ref %build-inputs "tcl")
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"/lib")
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(string-append "--with-tk="
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(assoc-ref %build-inputs "tk")
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"/lib"))))
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(synopsis "Waveform viewer for FPGA simulator trace files")
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(description "This package is a waveform viewer for FPGA
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simulator trace files (@dfn{FST}).")
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(home-page "https://gtkwave.sourceforge.net/")
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;; Exception against free government use in tcl_np.c and tcl_np.h.
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(license (list license:gpl2+ license:expat license:tcl/tk))))
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(define-public python-migen
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(package
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(name "python-migen")
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(version "0.9.2")
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||
(source
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||
(origin
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||
;; Tests fail in the PyPI tarball due to missing files.
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||
(method git-fetch)
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||
(uri (git-reference
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||
(url "https://github.com/m-labs/migen")
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||
(commit version)))
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||
(file-name (git-file-name name version))
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||
(sha256
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(base32 "1kq11if64zj84gv4w1q7l16fp17xjxl2wv5hc9dibr1z3m1gy67l"))))
|
||
(build-system python-build-system)
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||
(propagated-inputs
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||
(list python-colorama))
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||
(home-page "https://m-labs.hk/gateware/migen/")
|
||
(synopsis "Python toolbox for building complex digital hardware")
|
||
(description
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||
"Migen FHDL is a Python library that replaces the event-driven
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paradigm of Verilog and VHDL with the notions of combinatorial and
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synchronous statements, has arithmetic rules that make integers always
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behave like mathematical integers, and allows the design's logic to be
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constructed by a Python program.")
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(license license:bsd-2)))
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|
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(define-public python-myhdl
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(package
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||
(name "python-myhdl")
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||
(version "0.11")
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||
(source
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||
(origin
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||
(method url-fetch)
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||
(uri (pypi-uri "myhdl" version))
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||
(sha256
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||
(base32
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"04fi59cyn5dsci0ai7djg74ybkqfcjzhj1jfmac2xanbcrw9j3yk"))))
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(build-system python-build-system)
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(home-page "https://www.myhdl.org/")
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||
(synopsis "Python as a Hardware Description Language")
|
||
(description "This package provides a library to turn Python into
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a hardware description and verification language.")
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(license license:lgpl2.1+)))
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(define-public nvc
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(package
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(name "nvc")
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(version "1.9.2")
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(source (origin
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(method git-fetch)
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(uri (git-reference
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||
(url "https://github.com/nickg/nvc.git")
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(commit (string-append "r" version))))
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(file-name (string-append name "-" version "-checkout"))
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||
(sha256
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||
(base32
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"0zifyn7fr4k73ga6iwvsbsl6gi5106vlv5mkmqs0svi0sqx847f4"))))
|
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(build-system gnu-build-system)
|
||
(arguments
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`(#:out-of-source? #t
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||
#:configure-flags
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'("--enable-vhpi")
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||
#:phases
|
||
(modify-phases %standard-phases
|
||
(add-after 'unpack 'clean-up
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||
(lambda _
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(delete-file "autogen.sh"))))))
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||
(native-inputs
|
||
(list automake
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||
autoconf
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||
flex
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||
gnu-gettext
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||
libtool
|
||
pkg-config
|
||
which
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||
check)) ; for the tests
|
||
(inputs
|
||
(list elfutils
|
||
llvm-9
|
||
libffi))
|
||
(synopsis "VHDL compiler and simulator")
|
||
(description "This package provides a VHDL compiler and simulator.")
|
||
(home-page "https://www.nickg.me.uk/nvc/")
|
||
(license license:gpl3+)))
|
||
|
||
(define-public systemc
|
||
(package
|
||
(name "systemc")
|
||
(version "2.3.3")
|
||
(source
|
||
(origin
|
||
(method url-fetch)
|
||
(uri (string-append
|
||
"https://accellera.org/images/downloads/standards/"
|
||
"systemc/systemc-" version ".tar.gz"))
|
||
(sha256
|
||
(base32 "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap"))))
|
||
(native-inputs (list perl))
|
||
(build-system gnu-build-system)
|
||
(arguments '(#:configure-flags '("--enable-debug")))
|
||
(home-page "https://accellera.org/community/systemc")
|
||
(synopsis "Library for event-driven simulation")
|
||
(description
|
||
"SystemC is a C++ library for modeling concurrent systems, and the
|
||
reference implementation of IEEE 1666-2011. It provides a notion of timing as
|
||
well as an event-driven simulations environment. Due to its concurrent and
|
||
sequential nature, SystemC allows the description and integration of complex
|
||
hardware and software components. To some extent, SystemC can be seen as
|
||
a Hardware Description Language. However, unlike VHDL or Verilog, SystemC
|
||
provides sophisticated mechanisms that offer high abstraction levels on
|
||
components interfaces. This, in turn, facilitates the integration of systems
|
||
using different abstraction levels.")
|
||
;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
|
||
(license license:asl2.0)))
|
||
|
||
(define-public verilator
|
||
(package
|
||
(name "verilator")
|
||
(version "4.204")
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/verilator/verilator")
|
||
(commit (string-append "v" version))))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "0cji5c8870h895l2vxnz8g6z7msv23dzbjaf98va7kva0qlfy2fz"))))
|
||
(native-inputs
|
||
`(("autoconf" ,autoconf)
|
||
("automake" ,automake)
|
||
("bison" ,bison)
|
||
("flex" ,flex)
|
||
("gettext" ,gettext-minimal)
|
||
("python" ,python)))
|
||
(inputs
|
||
(list perl systemc))
|
||
(build-system gnu-build-system)
|
||
(arguments
|
||
'(#:configure-flags
|
||
(list (string-append "LDFLAGS=-L"
|
||
(assoc-ref %build-inputs "systemc")
|
||
"/lib-linux64"))
|
||
#:make-flags
|
||
(list (string-append "LDFLAGS=-L"
|
||
(assoc-ref %build-inputs "systemc")
|
||
"/lib-linux64"))
|
||
#:phases
|
||
(modify-phases %standard-phases
|
||
(replace 'bootstrap
|
||
(lambda _ (invoke "autoconf"))))
|
||
#:test-target "test"))
|
||
;; #error "Something failed during ./configure as config_build.h is incomplete.
|
||
;; Perhaps you used autoreconf, don't." -- so we won't. ^^
|
||
(home-page "https://www.veripool.org/projects/verilator/")
|
||
(synopsis "Fast Verilog/SystemVerilog simulator")
|
||
(description
|
||
"Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
|
||
It ``Verilates'' the specified Verilog or SystemVerilog code by reading it,
|
||
performing lint checks, and optionally inserting assertion checks and
|
||
coverage-analysis points. It outputs single- or multi-threaded @file{.cpp}
|
||
and @file{.h} files, the ``Verilated'' code.
|
||
|
||
The user writes a little C++/SystemC wrapper file, which instantiates the
|
||
Verilated model of the user’s top level module. These C++/SystemC files are
|
||
then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable
|
||
performs the design simulation. Verilator also supports linking its generated
|
||
libraries, optionally encrypted, into other simulators.")
|
||
(license license:lgpl3)))
|
||
|
||
(define-public fftgen
|
||
(let ((commit "1d75a992efd0528edea128a903aafdabe133cb08") ;no releases
|
||
(revision "0"))
|
||
(package
|
||
(name "fftgen")
|
||
(version (git-version "0" revision commit))
|
||
(source (origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/ZipCPU/dblclockfft")
|
||
(commit commit)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32
|
||
"0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
|
||
(build-system gnu-build-system)
|
||
(arguments
|
||
`(#:tests? #f ;no tests
|
||
#:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
|
||
#:phases (modify-phases %standard-phases
|
||
(delete 'configure)
|
||
(replace 'install
|
||
(lambda* (#:key outputs #:allow-other-keys)
|
||
(let ((bin (string-append (assoc-ref outputs "out")
|
||
"/bin")))
|
||
(install-file "sw/fftgen" bin)))))))
|
||
(synopsis "Generic pipelined FFT core generator")
|
||
(description "fftgen produces @acronym{FFT, fast-Fourier transforms}
|
||
hardware designs in Verilog.")
|
||
(home-page "https://zipcpu.com/")
|
||
(license license:lgpl3+))))
|
||
|
||
(define-public openfpgaloader
|
||
(package
|
||
(name "openfpgaloader")
|
||
(version "0.9.0")
|
||
(source (origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/trabucayre/openFPGALoader.git")
|
||
(commit (string-append "v" version))))
|
||
(file-name (string-append name "-" version "-checkout"))
|
||
(sha256
|
||
(base32
|
||
"1v3bwzhsrnsn304cqhd5azn68cl847qv8w8cb8bl7372jiqz5wqq"))))
|
||
(build-system cmake-build-system)
|
||
(native-inputs
|
||
(list pkg-config))
|
||
(inputs
|
||
(list libftdi libusb hidapi zlib))
|
||
(arguments
|
||
`(#:tests? #f)) ; No tests exist
|
||
(synopsis "Utility for programming FPGA")
|
||
(description "This package provides a program to transfer a bitstream
|
||
to an FPGA.")
|
||
(home-page "https://f4pga.org/")
|
||
(license license:asl2.0)))
|