fef3cfaaab
* gnu/packages/patches/qemu-CVE-2015-4037.patch, gnu/packages/patches/qemu-CVE-2015-4103.patch, gnu/packages/patches/qemu-CVE-2015-4104.patch, gnu/packages/patches/qemu-CVE-2015-4105.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt1.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt2.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt3.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt4.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt5.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt6.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt7.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt8.patch: New files. * gnu-system.am (dist_patch_DATA): Add them. * gnu/packages/qemu.scm (qemu-headless)[source]: Add patches.
81 lines
3 KiB
Diff
81 lines
3 KiB
Diff
From d61bb2482dc0c7426f451f23ba7e2748ae2cc06d Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 2 Jun 2015 15:07:01 +0000
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Subject: [PATCH] xen/pt: consolidate PM capability emu_mask
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There's no point in xen_pt_pmcsr_reg_{read,write}() each ORing
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PCI_PM_CTRL_STATE_MASK and PCI_PM_CTRL_NO_SOFT_RESET into a local
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emu_mask variable - we can have the same effect by setting the field
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descriptor's emu_mask member suitably right away. Note that
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xen_pt_pmcsr_reg_write() is being retained in order to allow later
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patches to be less intrusive.
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This is a preparatory patch for XSA-131.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
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Acked-by: Ian Campbell <ian.campbell@citrix.com>
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---
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hw/xen/xen_pt_config_init.c | 25 ++++---------------------
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1 file changed, 4 insertions(+), 21 deletions(-)
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diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
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index 436d0fd..516236a 100644
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--- a/hw/xen/xen_pt_config_init.c
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+++ b/hw/xen/xen_pt_config_init.c
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@@ -933,38 +933,21 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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* Power Management Capability
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*/
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-/* read Power Management Control/Status register */
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-static int xen_pt_pmcsr_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
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- uint16_t *value, uint16_t valid_mask)
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-{
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- XenPTRegInfo *reg = cfg_entry->reg;
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- uint16_t valid_emu_mask = reg->emu_mask;
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-
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- valid_emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
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-
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- valid_emu_mask = valid_emu_mask & valid_mask;
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- *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
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-
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- return 0;
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-}
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/* write Power Management Control/Status register */
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static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
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XenPTReg *cfg_entry, uint16_t *val,
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uint16_t dev_value, uint16_t valid_mask)
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{
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XenPTRegInfo *reg = cfg_entry->reg;
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- uint16_t emu_mask = reg->emu_mask;
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uint16_t writable_mask = 0;
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uint16_t throughable_mask = 0;
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- emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
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-
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/* modify emulate register */
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- writable_mask = emu_mask & ~reg->ro_mask & valid_mask;
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+ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
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cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
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/* create value for writing to I/O device register */
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- throughable_mask = ~emu_mask & valid_mask;
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+ throughable_mask = ~reg->emu_mask & valid_mask;
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*val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
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return 0;
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@@ -1000,9 +983,9 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = {
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.size = 2,
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.init_val = 0x0008,
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.ro_mask = 0xE1FC,
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- .emu_mask = 0x8100,
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+ .emu_mask = 0x810B,
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.init = xen_pt_common_reg_init,
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- .u.w.read = xen_pt_pmcsr_reg_read,
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+ .u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_pmcsr_reg_write,
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},
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{
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--
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2.2.1
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