gnu: yosys: Update to 0.26.
* gnu/packages/fpga.scm (yosys): Update to 0.26. [source]: Disable unnecessary recursive checkout. [arguments]<#:phases>: Expand "fix-paths" phase to match new version; remove obsolete "fix-iverilog-references" phase; add wrap phase. [inputs]: Add gtkwave, zlib, python, python-click. Signed-off-by: Christopher Baines <mail@cbaines.net>master
Simon South
Christopher Baines
parent
ade3bfd036
commit
8553148dfb
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@ -137,16 +137,15 @@ For synthesis, the compiler generates netlists in the desired format.")
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(define-public yosys
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(define-public yosys
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(package
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(package
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(name "yosys")
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(name "yosys")
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(version "0.9")
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(version "0.26")
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(source (origin
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(source (origin
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(method git-fetch)
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(method git-fetch)
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(uri (git-reference
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(uri (git-reference
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(url "https://github.com/YosysHQ/yosys")
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(url "https://github.com/YosysHQ/yosys")
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(commit (string-append "yosys-" version))
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(commit (string-append "yosys-" version))))
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(recursive? #t))) ; for the ‘iverilog’ submodule
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(sha256
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(sha256
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(base32
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(base32
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"0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
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"0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
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(file-name (git-file-name name version))))
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(file-name (git-file-name name version))))
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(build-system gnu-build-system)
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(build-system gnu-build-system)
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(arguments
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(arguments
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@ -162,7 +161,11 @@ For synthesis, the compiler generates netlists in the desired format.")
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(substitute* "./backends/smt2/smtio.py"
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(substitute* "./backends/smt2/smtio.py"
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(("\\['z3")
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(("\\['z3")
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(string-append "['" (search-input-file inputs "/bin/z3"))))
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(string-append "['" (search-input-file inputs "/bin/z3"))))
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(substitute* "./passes/cmds/show.cc"
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(substitute* "./kernel/fstdata.cc"
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(("vcd2fst")
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(search-input-file inputs "/bin/vcd2fst")))
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(substitute* '("./passes/cmds/show.cc"
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"./passes/cmds/viz.cc")
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(("exec xdot")
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(("exec xdot")
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(string-append "exec " (search-input-file inputs
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(string-append "exec " (search-input-file inputs
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"/bin/xdot")))
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"/bin/xdot")))
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@ -179,26 +182,6 @@ For synthesis, the compiler generates netlists in the desired format.")
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(("ABCEXTERNAL \\?=")
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(("ABCEXTERNAL \\?=")
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(string-append "ABCEXTERNAL = "
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(string-append "ABCEXTERNAL = "
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(search-input-file inputs "/bin/abc"))))))
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(search-input-file inputs "/bin/abc"))))))
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(add-before 'check 'fix-iverilog-references
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(lambda* (#:key inputs native-inputs #:allow-other-keys)
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(let ((iverilog (search-input-file (or native-inputs inputs)
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"/bin/iverilog")))
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(substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
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"./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
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"./techlibs/ice40/tests/test_bram.sh"
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"./techlibs/ice40/tests/test_ffs.sh"
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"./techlibs/xilinx/tests/bram1.sh"
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"./techlibs/xilinx/tests/bram2.sh"
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"./tests/bram/run-single.sh"
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"./tests/realmath/run-test.sh"
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"./tests/simple/run-test.sh"
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"./tests/techmap/mem_simple_4x1_runtest.sh"
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"./tests/tools/autotest.sh"
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"./tests/vloghtb/common.sh")
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(("if ! which iverilog") "if ! true")
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(("iverilog ") (string-append iverilog " "))
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(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
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iverilog "\""))))))
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(add-after 'install 'add-symbolic-link
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(add-after 'install 'add-symbolic-link
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(lambda* (#:key inputs #:allow-other-keys)
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(lambda* (#:key inputs #:allow-other-keys)
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;; Previously this package provided a copy of the "abc"
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;; Previously this package provided a copy of the "abc"
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@ -206,7 +189,11 @@ For synthesis, the compiler generates netlists in the desired format.")
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;; symbolic link so any external uses of that name continue to
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;; symbolic link so any external uses of that name continue to
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;; work.
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;; work.
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(symlink (search-input-file inputs "/bin/abc")
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(symlink (search-input-file inputs "/bin/abc")
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(string-append #$output "/bin/yosys-abc")))))))
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(string-append #$output "/bin/yosys-abc"))))
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(add-after 'install 'wrap
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(lambda* (#:key inputs #:allow-other-keys)
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(wrap-program (string-append #$output "/bin/yosys-witness")
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`("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
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(native-inputs
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(native-inputs
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(list bison
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(list bison
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flex
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flex
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@ -218,12 +205,16 @@ For synthesis, the compiler generates netlists in the desired format.")
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(inputs
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(inputs
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(list abc
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(list abc
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graphviz
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graphviz
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gtkwave
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libffi
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libffi
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psmisc
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psmisc
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readline
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readline
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tcl
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tcl
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xdot
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xdot
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z3))
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z3
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zlib
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python
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python-click))
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(home-page "https://yosyshq.net/yosys/")
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(home-page "https://yosyshq.net/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(description "Yosys synthesizes Verilog-2005.")
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